1. Field of the Invention
The present invention relates to a semiconductor device molded in resin wherein a plurality of semiconductor chips and passive parts are mounted within one semiconductor device molded in resin and to a manufacturing method for the same. The present invention relates, in particular, to a semiconductor device molded in resin wherein two semiconductor chips are stacked and mounted on a wiring board and to a manufacturing method for the same.
2. Description of the Background Art
In recent years reduction in the weight and thickness of mobile apparatuses, as represented by notebook personal computers, cellular phones, and the like, has rapidly progressed. According to such a trend an increase in the density of electronic parts and an enhancement in performance are required for electronic parts mounted on the mother boards of the apparatuses, in particular, for semiconductor devices, which make up the core of the apparatuses. Conventionally an MCM (multichip module) wherein a plurality of semiconductor chips is mounted on a plane surface of an interposer (substrate having external terminals for direct mounting on a mother board), for example, is generally used (see Japanese unexamined patent publication H09 (1997)-8220 (FIG. 1)) in the case wherein a plurality of semiconductor chips is incorporated within one semiconductor device. Moreover, in order to further increase the configuration density within the semiconductor device, a method of stacking semiconductor chips, for example, has come into wide use (see Japanese unexamined patent publication H11 (1999)-204720 (FIGS. 1 and 3)). The size of a semiconductor chip mounted above the lower chip is, in general, smaller than the lower chip to make connection of fine metal wires easy in the case wherein a plurality of semiconductor chips is stacked in a conventional manner. In some cases, however, the dimensions of the upper semiconductor chip are greater than that of the lower chip in the configuration wherein the lower chip is, for example, directly bonded to a board and the upper semiconductor chip is mounted on the lower chip so that the electric circuit thereof faces upward (see Japanese unexamined patent publication 2000-299431 (FIG. 1) and Japanese unexamined patent publication 2001-320014 (FIG. 1)). These cases disclose a technique of supporting the upper chip with supports, or support members.
The upper semiconductor chip is larger than the lower semiconductor chip and the upper semiconductor chip is in a condition extending in an overhanging manner over the lower semiconductor chip, which is a flip chip, in a conventional semiconductor device molded in resin having a configuration wherein the lower semiconductor chip is directly flip chip bonded to a carrier board and the upper semiconductor chip is mounted on the lower chip with the electric circuit thereof facing upward. In this case microcracks may occur in the upper semiconductor chip or defective connections of fine metal wires may occur due to impact at the time of connection of fine metal wires to the upper semiconductor chip by means of an ultrasonic wave or thermocompression bonding method.
Here, a problem is described in reference to FIGS. 10A and 10B. FIG. 10A is a cross sectional view showing a conventional semiconductor device molded in resin and FIG. 10B shows an enlarged view of a portion of FIG. 10A. In addition, the enlarged view shows the phenomenon that is the problem. In a semiconductor device molded in resin having a configuration wherein first semiconductor chip 1, is directly flip chip bonded to a carrier board 20 and a second semiconductor chip 2 is mounted on first semiconductor chip 1 so that the electric circuit thereof faces upward, Au wires 7 are connected to electrode pads 4 of second semiconductor chip 2 using capillary 10, as shown in FIGS. 10A and 10B. At this time second semiconductor chip 2 bends symbol (11 indicates the amount of bending Δh) due to the impact from the load when ball bonding is carried out while ultrasonic waves and the load are being applied to an electrode pad 4 at a high temperature (from 150° C. to 250° C.) in the case wherein second semiconductor chip 2 is significantly larger than first semiconductor chip 1. Therefore, a microscopic crack 12 occurs in the case wherein an Au wire 7 cannot be stably bonded or in the case wherein the load is too great. Stud bumps are denoted by symbol 5, conductive paste is denoted by symbol 6, underfill resin is denoted by symbol 13 and adhesive is denoted by symbol 14 in FIGS. 10A and 10B.